The present invention relates to a method of forming a micro pattern of a semiconductor device and, more particularly, to a method of forming a micro pattern as it applies to the formation of DRAM bit line contact holes.
As the integration level of semiconductor devices is increased, a minimum line width gradually shrinks. Several process methods are employed in order to implement a desired micro line width due to the higher integration of devices.
However, a micro pattern formed using a spacer is applicable to only a line and space pattern. In particular, the micro pattern can be applied to a case where the patterns of a cell gate region have a very simple pattern, such as NAND flash memory devices, or a 2-dimensional array having an excellent regularity. If a Double Exposure & Etch Technique (DEET) method is used, a bit line contact hole pattern of a DRAM can be formed, but a Critical Dimension (CD) becomes irregular due to overlay problem. Further, since a mask formation process has to be performed twice, the production cost is increased.